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Proceedings Paper

Patterning strategy and performance of 1.3NA tool for 32nm node lithography
Author(s): Shoji Mimotogi; Masaki Satake; Yosuke Kitamura; Kazuhiro Takahata; Katsuyoshi Kodera; Hiroharu Fujise; Tatsuhiko Ema; Koutaro Sho; Kazutaka Ishigo; Takuya Kono; Masafumi Asano; Kenji Yoshida; Hideki Kanai; Suigen Kyoh; Hideaki Harakawa; Akiko Nomachi; Tatsuya Ishida; Katsura Miyashita; Soichi Inoue
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Paper Abstract

We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um2 area is clearly resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability. There is no immersion induced defects.

Paper Details

Date Published: 1 April 2008
PDF: 9 pages
Proc. SPIE 6924, Optical Microlithography XXI, 69240M (1 April 2008); doi: 10.1117/12.772201
Show Author Affiliations
Shoji Mimotogi, Toshiba Corp. (Japan)
Masaki Satake, Toshiba Corp. (Japan)
Yosuke Kitamura, Toshiba Corp. (Japan)
Kazuhiro Takahata, Toshiba Corp. (Japan)
Katsuyoshi Kodera, Toshiba Corp. (Japan)
Hiroharu Fujise, Toshiba Corp. (Japan)
Tatsuhiko Ema, Toshiba Corp. (Japan)
Koutaro Sho, Toshiba Corp. (Japan)
Kazutaka Ishigo, Toshiba Corp. (Japan)
Takuya Kono, Toshiba Corp. (Japan)
Masafumi Asano, Toshiba Corp. (Japan)
Kenji Yoshida, Toshiba Corp. (Japan)
Hideki Kanai, Toshiba Corp. (Japan)
Suigen Kyoh, Toshiba Corp. (Japan)
Hideaki Harakawa, Toshiba Corp. (Japan)
Akiko Nomachi, Toshiba Corp. (Japan)
Tatsuya Ishida, Toshiba Corp. (Japan)
Katsura Miyashita, Toshiba Corp. (Japan)
Soichi Inoue, Toshiba Corp. (Japan)

Published in SPIE Proceedings Vol. 6924:
Optical Microlithography XXI
Harry J. Levinson; Mircea V. Dusa, Editor(s)

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