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Proceedings Paper

Negative and iterated spacer lithography processes for low variability and ultra-dense integration
Author(s): Andrew Carlson; Tsu-Jae King Liu
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Paper Abstract

Variation in the critical dimension (CD) of a transistor is a primary concern for advanced lithography. Because variation from sources such as corner rounding or line edge roughness does not scale with CD, variability in transistor performance increases with scaling and may impact the timing or even the functionality of critical circuits such as static random access memories (SRAM) and ring oscillators. Spacer lithography is an attractive patterning method for future technology nodes, because its use of a very uniform and controllable chemical vapor deposition (CVD) step allows for the definition of very narrow lines with low variation and reduced pitch1,2. In practice, however, the possible pitch reductions are limited by the need for conventional lithography to produce negative features (e.g., trenches and holes) and increasing CD variability with iterated spacer processing. In this work, an extension to spacer lithography is presented to overcome these limitations. Negative features down to 30nm in width are fabricated using spacer-defined features. A multi-tiered hard mask process is also presented to enable eight-fold pitch reduction with no increase in CD variation. In combination, these processes enable ultra-dense circuit integration for regular layouts.

Paper Details

Date Published: 11 April 2008
PDF: 9 pages
Proc. SPIE 6924, Optical Microlithography XXI, 69240B (11 April 2008); doi: 10.1117/12.772049
Show Author Affiliations
Andrew Carlson, Univ. of California at Berkeley (United States)
Tsu-Jae King Liu, Univ. of California at Berkeley (United States)


Published in SPIE Proceedings Vol. 6924:
Optical Microlithography XXI
Harry J. Levinson; Mircea V. Dusa, Editor(s)

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