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Proceedings Paper

Fabrication of 32-nm contact/via hole by photolithographic-friendly method
Author(s): Tetsu Kawasaki; Satoru Shimura; Fumiko Iwao; Eiichi Nishimura; Masato Kushibiki; Kazuhide Hasebe; Michael Carcasi; Mark Somervell; Steven Scheer; Hidetami Yaegashi
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Paper Abstract

As semiconductor design rules continue to shrink, studies have begun on the 32nm-node and 22nm-node generations in semiconductor lithography technology in conjunction with the development of various fine-processing technologies. Research has been especially active in the development of high-NA193nm immersion lithography and EUV lithography for 32nm processes and beyond, but at the present stage of development, many technical issues have been reported. For example, in the contact-hole and via-hole pattern formation process in 193nm immersion lithography, it is difficult to maintain good resolution performance and process margins compared to line and space patterns. Poor resolution and other defects in the lithography process are major factors behind reduced yields in semiconductor production lines, and to prevent such defects, studies have begun on double patterning technology and shrink technology applied after resist-hole-pattern formation. Here, however, the need for reducing production processes and production costs have become major issues. In response to these technical issues, we evaluated a variety of hole-shrink processes as candidates for a fine-hole-pattern formation technology, and as a result of this study, we succeeded in applying an original hole-shrink technology to the formation of 40nm hole patterns and beyond.

Paper Details

Date Published: 26 March 2008
PDF: 7 pages
Proc. SPIE 6923, Advances in Resist Materials and Processing Technology XXV, 692333 (26 March 2008); doi: 10.1117/12.771907
Show Author Affiliations
Tetsu Kawasaki, Tokyo Electron Kyushu Ltd. (Japan)
Satoru Shimura, Tokyo Electron Kyushu Ltd. (Japan)
Fumiko Iwao, Tokyo Electron Kyushu Ltd. (Japan)
Eiichi Nishimura, Tokyo Electron AT Ltd. (Japan)
Masato Kushibiki, Tokyo Electron AT Ltd. (Japan)
Kazuhide Hasebe, Tokyo Electron Tohoku Ltd. (Japan)
Michael Carcasi, Tokyo Electron America Ltd. (United States)
Mark Somervell, Tokyo Electron America Ltd. (United States)
Steven Scheer, Tokyo Electron America Ltd. (United States)
Hidetami Yaegashi, Tokyo Electron Ltd. (Japan)

Published in SPIE Proceedings Vol. 6923:
Advances in Resist Materials and Processing Technology XXV
Clifford L. Henderson, Editor(s)

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