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Proceedings Paper

Integration of pixelated phase masks for full-chip random logic layers
Author(s): Richard Schenker; Srinivas Bollepalli; Bin Hu; Kenny Toh; Vivek Singh; Karmen Yung; Wen-hao Cheng; Yan Borodovsky
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Paper Abstract

This work describes the advantages, tolerances and integration issues of using Pixelated Phase Masks for patterning logic interconnect layers. Pixelated Phase Masks (PPMs) can act as variable high-transmission attenuated phase shift masks where the pixelated phase configuration simultaneously optimizes OPC and SRAF generation. Thick mask effects help enable PPMs by allowing larger minimum pixel sizes and phase designs with near equal sized zero and piphase regions. PPMs with a 3-tone pixel mask (un-etched glass, etched glass, chrome) offer more flexible patterning capability compared to 2-tone pixel mask (no chrome) style but at the detriment of a more complex mask making process. We describe the issues and opportunities associated with using PPMs for patterning a 65nm generation first level metal layer of a micro-processor.

Paper Details

Date Published: 7 March 2008
PDF: 11 pages
Proc. SPIE 6924, Optical Microlithography XXI, 69240I (7 March 2008); doi: 10.1117/12.771677
Show Author Affiliations
Richard Schenker, Intel Corp. (United States)
Srinivas Bollepalli, Intel Corp. (United States)
Bin Hu, Intel Corp. (United States)
Kenny Toh, Intel Corp. (United States)
Vivek Singh, Intel Corp. (United States)
Karmen Yung, Intel Corp. (United States)
Wen-hao Cheng, Intel Corp. (United States)
Yan Borodovsky, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 6924:
Optical Microlithography XXI
Harry J. Levinson; Mircea V. Dusa, Editor(s)

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