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Proceedings Paper

Experimental evaluation of out-of-plane distortion of electrostatically chucked EUV reticle
Author(s): Kazuya Ota; Takao Taguchi; Mitsuaki Amemiya; Yasushi Nishiyama; Takashi Kamono; Naosuke Nishimura; Tadahiko Takikawa; Youichi Usui; Osamu Suga
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Paper Abstract

"Reticle protection during storage, handling and use" is one of the critical issues of EUV lithography because no practical pellicle has been found for EUV reticles as yet. The front surface of an EUV reticle has to be protected from particles larger than 20-30 nm to maintain the image quality on the wafer plane, and the backside also has to be protected to maintain the flatness of the reticle chucked on an electrostatic chuck (ESC). In this paper, we are focusing on particles on the backside of the reticle. If a particle lies between the reticle and the chuck, it has a strong impact on the flatness of the reticle, and the wafer overlay is degraded by out-of-plane distortion (OPD) and in-plane distortion (IPD) due to the particle1-5. From this point of view, we need to know the maximum permissible size of particles on the backside of the reticle. MIRAI-Selete introduced an experimental setup that can measure the flatness of the chucked reticle in a vacuum. An electrostatic chuck is installed in the vacuum chamber of Mask Protection Engineering Tool (MPE Tool)6, a reticle is automatically carried from a reticle pod to the chuck in the tool. The flatness of the reticle can be measured by an interferometer through a viewport underneath the chamber. We can measure the reticle flatness with 3-nm@rms reproducibility using this setup. We report results of experimental evaluation about the relationship between the reticle OPD, the size of particle and the chucking force of ESC.

Paper Details

Date Published: 21 March 2008
PDF: 8 pages
Proc. SPIE 6921, Emerging Lithographic Technologies XII, 69213S (21 March 2008); doi: 10.1117/12.771339
Show Author Affiliations
Kazuya Ota, Semiconductor Leading Edge Technologies, Inc. (Japan)
Takao Taguchi, Semiconductor Leading Edge Technologies, Inc. (Japan)
Mitsuaki Amemiya, Semiconductor Leading Edge Technologies, Inc. (Japan)
Yasushi Nishiyama, Semiconductor Leading Edge Technologies, Inc. (Japan)
Takashi Kamono, Semiconductor Leading Edge Technologies, Inc. (Japan)
Naosuke Nishimura, Semiconductor Leading Edge Technologies, Inc. (Japan)
Tadahiko Takikawa, Semiconductor Leading Edge Technologies, Inc. (Japan)
Youichi Usui, Semiconductor Leading Edge Technologies, Inc. (Japan)
Osamu Suga, Semiconductor Leading Edge Technologies, Inc. (Japan)


Published in SPIE Proceedings Vol. 6921:
Emerging Lithographic Technologies XII
Frank M. Schellenberg, Editor(s)

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