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Proceedings Paper

A routing clean-up methodology for improvement of defect and lithography related yield
Author(s): Jacques Herry; Reinhard März; Hanno Melzner; Kai Peter; Olivier Rizzo
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Paper Abstract

Particle induced defects are still one of the major sources of yield loss in semiconductor manufacturing. In addition, optical distortion of shapes cannot be ignored in modern technologies and requires increasing design effort in order to avoid yield loss and minimize manufacturing costs. Although suppliers of automated routing tools are increasingly addressing these issues, we still see significant improvement potential even in layouts produced by routers attributed as DfM aware. We propose a post-routing clean-up step to address both defect and lithography related yield loss in the routing layers. In contrast to a "find and fix" approach, this methodology creates lithography friendly layout "by construction", based on the general concept of shape simplification and standardization.

Paper Details

Date Published: 4 March 2008
PDF: 11 pages
Proc. SPIE 6925, Design for Manufacturability through Design-Process Integration II, 69250J (4 March 2008); doi: 10.1117/12.770292
Show Author Affiliations
Jacques Herry, Infineon Technologies France (France)
Reinhard März, Infineon Technologies (Germany)
Hanno Melzner, Infineon Technologies (Germany)
Kai Peter, Infineon Technologies (Germany)
Olivier Rizzo, Infineon Technologies France (France)


Published in SPIE Proceedings Vol. 6925:
Design for Manufacturability through Design-Process Integration II
Vivek K. Singh; Michael L. Rieger, Editor(s)

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