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Proceedings Paper

Electron-beam-patterning simulation and metrology of complex layouts on Si/Mo multilayer substrates
Author(s): G. P. Patsis; D. Drygiannakis; N. Tsikrikas; I. Raptis; E. Gogolides
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Paper Abstract

Strong candidate lithography for the mass production of devices at the 32nm technology node and beyond is extreme ultra violet lithography (EUVL). The mask used in EUVL is a complex set of layers. The material composition and thickness of each layer should be considered explicitly in an attempt to model the deposited energy in the resist film during fabrication of mask features using electron-beam lithography. Targeting to sub-32nm technology even with the reduction by 4 of the mask features on the wafer level, lithography should consider accurate fabrication features on the mask level of the order of 50nm. Therefore, detailed simulation of the electron-beam fabrication process, as well as the resist dissolution mechanism and etching is demanding. In this work an attempt is initiated targeting in combining two simulation techniques i.e., the electron-beam simulation, with the stochastic lithography simulation, in a common simulation platform. This way it will be possible to get detailed information of the fine details of the fabricated features, taking into account the multilayer substrate of the mask, and the resist material properties. The e-beam simulation algorithm is presented and used to expose a layout. The calculated energy deposition in the resist level, initially determined considering resist material to be continuous, is used in the discrete representation of the resist. With appropriate threshold in the exposure energy, also acid diffusion could be taken into consideration. Stochastic development of the resist material, delivers line-edge roughness (LER) and critical dimension (CD) on the resist level, in terms of polymer chain architecture.

Paper Details

Date Published: 24 March 2008
PDF: 8 pages
Proc. SPIE 6922, Metrology, Inspection, and Process Control for Microlithography XXII, 69222K (24 March 2008); doi: 10.1117/12.769392
Show Author Affiliations
G. P. Patsis, Institute of Microelectronics (Greece)
D. Drygiannakis, Institute of Microelectronics (Greece)
N. Tsikrikas, Institute of Microelectronics (Greece)
National Technical Univ. of Athens (Greece)
I. Raptis, Institute of Microelectronics (Greece)
E. Gogolides, Institute of Microelectronics (Greece)


Published in SPIE Proceedings Vol. 6922:
Metrology, Inspection, and Process Control for Microlithography XXII
John A. Allgair; Christopher J. Raymond, Editor(s)

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