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Proceedings Paper

A memory and MHZ efficient EDMA transfer scheme for video encoding algorithms on TI TMS320DM642
Author(s): Noha A. El-Yamany
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Paper Abstract

Video encoding algorithms require processing of data arranged in blocks of pixels. For efficient computation, pixel blocks are expected to be stored contiguously in memory, and within each block, pixels are to be arranged in a raster scan (left to right, top to bottom order). Since data captured from the video port is linearly arranged in memory (one line after the other), it is necessary to arrange the data in the two-dimensional form before processing for encoding. A common approach to achieve the two-dimensional arrangement is through optimized functions (in C or Assembly) to arrange the captured data, which is stored in an intermediate buffer, into an input buffer from which it is ready for encoding. However, this approach has two main drawbacks. First, a portion of the CPU MHZ budget is consumed only on data arrangement. Second, an intermediate data buffer is required to hold the data before the arrangement into the input buffer takes place, and hence increasing the memory requirements. In this paper, a memory and MHZ efficient EDMA transfer scheme is introduced for simultaneous data transfer and two-dimensional arrangement from the video port to the DSP memory. The proposed scheme is described in details for TI TMS320DM642TM.

Paper Details

Date Published: 26 February 2008
PDF: 9 pages
Proc. SPIE 6811, Real-Time Image Processing 2008, 68110K (26 February 2008); doi: 10.1117/12.767854
Show Author Affiliations
Noha A. El-Yamany, Southern Methodist Univ. (United States)


Published in SPIE Proceedings Vol. 6811:
Real-Time Image Processing 2008
Nasser Kehtarnavaz; Matthias F. Carlsohn, Editor(s)

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