Share Email Print

Proceedings Paper

Architecture-template for massively parallel statistical image processing models
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

The System-on-Chip design of specific image analysis architectures, which are based on massively parallel Markov Random Field (MRF) processing principles is so far an unstructured, faultprone and complex task. Up to now neither a systematically derived architecture-template nor an industrial approved tool-chain is available to support the VLSI design task for these kind of digital architectures. In this contribution, we report on a theoretical sound and systematically derived architecture-template for massively parallel MRF processing devices. The paper is finalized by prototypical implementations of selected architecture parts using FPGA technologies. These results demonstrate the capability of the proposed architecture-template and manifest the industrial relevance of the template.

Paper Details

Date Published: 26 February 2008
PDF: 17 pages
Proc. SPIE 6811, Real-Time Image Processing 2008, 68110I (26 February 2008); doi: 10.1117/12.767664
Show Author Affiliations
Stephan C. Stilkerich, EADS Innovation Works (Germany)

Published in SPIE Proceedings Vol. 6811:
Real-Time Image Processing 2008
Nasser Kehtarnavaz; Matthias F. Carlsohn, Editor(s)

© SPIE. Terms of Use
Back to Top