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Proceedings Paper

An implementation of a multiplierless Hough transform on an FPGA platform using hybrid-log arithmetic
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Paper Abstract

This paper describes an implementation of the Hough Transform (HT) that uses a hybrid-log structure for the main arithmetic components instead of fixed or floating point architectures. A major advantage of this approach is a reduction in the overall computational complexity of the HT without adversely affecting its overall performance when compared to fixed point solutions. The proposed architecture is compatible with the latest FPGA architectures allowing multiple units to operate in parallel without exhausting the dedicated (but limited) on-chip signal processing resources that can instead be allocated to other image processing and classification tasks. The solution proposed is capable of performing a real-time HT on megapixel images at frame rates of up to 25 frames per second using a Xilinx VirtexTM architecture.

Paper Details

Date Published: 26 February 2008
PDF: 10 pages
Proc. SPIE 6811, Real-Time Image Processing 2008, 68110G (26 February 2008); doi: 10.1117/12.766459
Show Author Affiliations
Peter Lee, Univ. of Kent (United Kingdom)
Evangelos Alexiadis, Univ. of Kent (United Kingdom)


Published in SPIE Proceedings Vol. 6811:
Real-Time Image Processing 2008
Nasser Kehtarnavaz; Matthias F. Carlsohn, Editor(s)

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