Share Email Print

Proceedings Paper

An optimum design of the LOFIC CMOS image sensor for high sensitivity, low noise, and high full well capacity
Author(s): Nana Akahane; Woonghee Lee; Shigetoshi Sugawa
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

It is indispensable for high quality image sensors to have performances of high sensitivity, low noise, high full well capacity and good linear response. The CMOS image sensor with the lateral overflow integration capacitor (LOFIC) has been accomplishing these performances because of its wide dynamic range capability in one exposure. Recently, we have improved the SNR of the LOFIC CMOS image sensor and achieved the number of input-referred noise electrons of 2 e- or below without any column amplifier circuits by increasing the photo-electric conversion gain at the floating diffusion (FD) in pixel as keeping low dark current, good uniformity and high well capacity. It is clear that the relation among the conversion gain, the SNR and the full well capacity decides the optimum design for the FD capacitance and the LOFIC to realize a high quality image sensor. In this paper, the optimum design method of the LOFIC CMOS image sensor for high sensitivity, low noise and high full well capacity is discussed through theoretical analysis and experiments by using the fabricated LOFIC CMOS image sensor.

Paper Details

Date Published: 21 February 2008
PDF: 8 pages
Proc. SPIE 6817, Digital Photography IV, 681702 (21 February 2008); doi: 10.1117/12.765649
Show Author Affiliations
Nana Akahane, Tohoku Univ. (Japan)
Woonghee Lee, Tohoku Univ. (Japan)
Shigetoshi Sugawa, Tohoku Univ. (Japan)

Published in SPIE Proceedings Vol. 6817:
Digital Photography IV
Jeffrey M. DiCarlo; Brian G. Rodricks, Editor(s)

© SPIE. Terms of Use
Back to Top