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Proceedings Paper

Micromachining of a fiber-to-waveguide coupler using grayscale lithography and through-wafer etch
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Paper Abstract

For some time, the micro-optics and photonics fields have relied on fabrication processes and technology borrowed from the well-established silicon integrated circuit industry. However, new fabrication methodologies must be developed for greater flexibility in the machining of micro-optic devices. To this end, we have explored grayscale lithography as an enabler for the realization of such devices. This process delivers the ability to sculpt materials arbitrarily in three dimensions, thus providing the flexibility to realize optical surfaces to shape, transform, and redirect the propagation of light efficiently. This has opened the door for new classes of optical devices. As such, we present a fiber-to-waveguide coupling structure utilizing a smoothly contoured lensing surface in the device layer of a silicon-on insulator (SOI) wafer, fabricated using grayscale lithography. The structure collects light incident normally to the wafer from a singlemode optical fiber plugged through the back surface and turns the light into the plane of the device layer, focusing it into a single-mode waveguide. The basis of operation is total internal reflection, and the device therefore has the potential advantages of providing a large bandwidth, low polarization sensitivity, high efficiency, and small footprint. The structure was optimized with a simulated annealing algorithm in conjunction with two-dimensional finite-difference time-domain (FDTD) simulation accelerated on the graphics processing unit (GPU), and achieves a theoretical efficiency of approximately seventy percent, including losses due to Fresnel reflection from the oxide/silicon interface. Initial fabrication results validate the principle of operation. We discuss the grayscale fabrication process as well as the through-wafer etch for mechanical stabilization and alignment of the optical fiber to the coupling structure. Refinement of the through-wafer etch process for high etch rate and appropriate sidewall taper are addressed.

Paper Details

Date Published: 26 February 2008
PDF: 10 pages
Proc. SPIE 6882, Micromachining and Microfabrication Process Technology XIII, 688206 (26 February 2008); doi: 10.1117/12.764036
Show Author Affiliations
Thomas Dillon, Univ. of Delaware (United States)
Mathew Zablocki, Univ. of Delaware (United States)
Shouyan Shi, Univ. of Delaware (United States)
Janusz Murakowski, Univ. of Delaware (United States)
Dennis Prather, Univ. of Delaware (United States)

Published in SPIE Proceedings Vol. 6882:
Micromachining and Microfabrication Process Technology XIII
Mary-Ann Maher; Jung-Chih Chiao; Paul J. Resnick, Editor(s)

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