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Proceedings Paper

A CAD tool for the automatic generation of synthesizable parallel prefix adders in VHDL
Author(s): Konstantinos Vitoroulis; Tadeusz Obuchowicz; Asim J. Al-Khalili
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Paper Abstract

In this paper we present a CAD tool capable of generating a variety of parallel prefix adders described in the VHDL language. The VHDL code generated by the tool is synthesizable and the resulting adders can be used as design components in an automatic or semi-custom design flow. In its current version the tool is able to generate arbitrary bit-size prefix adders of the following types: Sklansky, Ladner-Fischer, Kogge-Stone, Han-Carlson, Brent-Kung and Knowles.

Paper Details

Date Published: 21 December 2007
PDF: 12 pages
Proc. SPIE 6798, Microelectronics: Design, Technology, and Packaging III, 67980Q (21 December 2007); doi: 10.1117/12.759454
Show Author Affiliations
Konstantinos Vitoroulis, Concordia Univ. (Canada)
Tadeusz Obuchowicz, Concordia Univ. (Canada)
Asim J. Al-Khalili, Concordia Univ. (Canada)


Published in SPIE Proceedings Vol. 6798:
Microelectronics: Design, Technology, and Packaging III
Alex J. Hariz; Vijay K. Varadan, Editor(s)

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