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Proceedings Paper

A 6-18.5 GHz dynamic frequency divider in 0.25µm SOI CMOS
Author(s): Leigh Milner
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Paper Abstract

An 18.5 GHz divide-by-four digital frequency divider has been implemented in 0.25μm silicon-on-sapphire CMOS with a power dissipation of 41mW, supply voltage of 2.75V and size of 40×60μm. The design utilises two cascaded divide-by-two 6 transistor dividers. A buffer is used at the output of the first stage to minimise the capacitive load and restore the signal amplitude for the second stage. This significantly increases the operating speed of the circuit. An optimisation design method is proposed for sizing the transistors that uses the amplitude of the output voltage as a metric for the divider speed.

Paper Details

Date Published: 21 December 2007
PDF: 5 pages
Proc. SPIE 6798, Microelectronics: Design, Technology, and Packaging III, 679806 (21 December 2007); doi: 10.1117/12.758883
Show Author Affiliations
Leigh Milner, Defence Science and Technology Organisation (Australia)


Published in SPIE Proceedings Vol. 6798:
Microelectronics: Design, Technology, and Packaging III
Alex J. Hariz; Vijay K. Varadan, Editor(s)

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