Share Email Print
cover

Proceedings Paper

SoC variability evaluation and reduction
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Device parameter variation across the product die and wafer compromises functionality, performance, and yield of integrated devices increasingly more as technology shrinks into the sub-100 nm range. Such variability is of special importance for System-on-Chip products, affecting e.g., frequency response of the analog/RF blocks. Variability reduction can be accomplished through tightening the manufacturing process, adding technology rules for manufacturability (Design-for-Manufacturability, DFM), or developing parameterized, correct by construction (CBC) design or layout (upstream approach). While so far the best option for variability reduction was to improve process capability without resticting product design (downstream approach), it may no longer be preferred due to the continuously increasing process cost driven by technology shrinks. In this work, we discuss a procedure to separate the variability for a 1D and 2D layout due to the lithography and other combined process effects. We then use this procedure to define design rules for analog/RF layout to minimize parametric variability at the minimal cost of the footprint. These rules can be subsequently used to create the CBC design and layout (upstream approach) such that the process window is traded for device footprint by the aggressiveness of the resolution enhancement techniques (e.g., optical proximity correction, OPC). Another option for variability reduction, the layout-time addition of design rules or OPC in response to the localized issues in a random layout (hot spots) causes reworks and delays and is not preferred.

Paper Details

Date Published: 28 December 2007
PDF: 8 pages
Proc. SPIE 6798, Microelectronics: Design, Technology, and Packaging III, 67980I (28 December 2007); doi: 10.1117/12.758782
Show Author Affiliations
Artur P. Balasinski, Cypress Semiconductor (United States)
Michael C. Smayling, Tela Innovations, Inc. (United States)
Valery Axelrad, Sequoia Design Systems, Inc. (United States)


Published in SPIE Proceedings Vol. 6798:
Microelectronics: Design, Technology, and Packaging III
Alex J. Hariz; Vijay K. Varadan, Editor(s)

© SPIE. Terms of Use
Back to Top