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Circuit implementation of a theoretical model of trap centres in GaAs and GaN devices
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Paper Abstract

A novel and simple circuit implementation of trap centres in GaAs and GaN HEMTs, MESFETs and HFETs is presented. When included in transistor models it explains the potential-dependent time constants seen in the circuit manifestations of charge trapping, being gate lag and drain overshoot. The implementation is suitable for both time- and harmonic-domain simulations. The trap-centre model is based on Shockley-Read-Hall (SRH)1 statistics of the trapping process. It also accommodates carrier injection from other important device effects, such as impact ionization and light sensitivity. In the model, the ionization charge of the trap centre is represented by the charge in a capacitor. The potential across the capacitor is proportional to the potential across the region of the trap centre in the semiconductor. It is positive or negative depending on the polarity of the ionization charge - electrons or holes. When included in a transistor model, this potential is added to the gate potential that controls the drain-current description. The capacitor is charged or discharged by two opposing currents that are functions of the ionization potential and temperature: one models charge emission; and the other, which is also controlled by an external potential and injected current, models charge capture. The external potential is typically a linear function of a transistor's terminal potentials. The injection current can model charge generated by light or by holes from impact ionization. The four parameters for the model are simply the signed potential of the trap centre when fully ionized, the time constant for charge emission at a specific temperature, the injection-current sensitivity, and the activation energy of the emission process. The latter is used to predict the temperature dependence of the emission rate. The capture rate is determined within the model by an exponential function of the external potential that controls capture. Thus the model elegantly predicts asymmetry between trap charging and discharging rates. The model accounts for variation in emission and capture rates with temperature, which is shown to vary significantly over typical transistor operating ranges.

Paper Details

Date Published: 21 December 2007
PDF: 11 pages
Proc. SPIE 6798, Microelectronics: Design, Technology, and Packaging III, 67980R (21 December 2007); doi: 10.1117/12.758711
Show Author Affiliations
James G. Rathmell, The Univ. of Sydney (Australia)
Anthony E. Parker, Macquarie Univ. (Australia)

Published in SPIE Proceedings Vol. 6798:
Microelectronics: Design, Technology, and Packaging III
Alex J. Hariz; Vijay K. Varadan, Editor(s)

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