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Proceedings Paper

Use of layout automation and design-based metrology for defect test mask design and verification
Author(s): Chris Spence; Cyrus Tabery; Andre Poock; Arndt C. Duerr; Thomas Witte; Jan Fiebig; Jan Heumann
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Paper Abstract

This paper studies the impact of shape and local environment (pattern layout) on the ability to detect defects on the reticle and the extent to which they affect the dimension of the printed image on the wafer. The authors have made extensive use of design information to perform a thorough evaluation. OPC software was used to generate mask data that was comparable to product mask data. Defects were placed on the post-OPC layout and OPC software was also used to simulate the dimension of the defective features as printed on the wafer. "Design Based Metrology" was used to create accurate metrology recipes to support wafer and mask metrology. Ultimately the procedures described in this paper allow a direct correlation to be made between reticle inspectability and the impact of the same defects on wafer CD. Data is presented for the case of the Contact Hole layer of a "65nm" Logic technology, though the methods described in the paper are applicable to all layers.

Paper Details

Date Published: 16 November 2007
PDF: 12 pages
Proc. SPIE 6730, Photomask Technology 2007, 67300P (16 November 2007); doi: 10.1117/12.746953
Show Author Affiliations
Chris Spence, AMD (United States)
Cyrus Tabery, AMD (United States)
Andre Poock, AMD Fab 36 LLC & Co. KG (Germany)
Arndt C. Duerr, AMTC GmbH & Co. KG (Germany)
Thomas Witte, AMTC GmbH & Co. KG (Germany)
Jan Fiebig, AMTC GmbH & Co. KG (Germany)
Jan Heumann, AMTC GmbH & Co. KG (Germany)


Published in SPIE Proceedings Vol. 6730:
Photomask Technology 2007
Robert J. Naber; Hiroichi Kawahira, Editor(s)

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