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Proceedings Paper

Non-uniform yield optimization for integrated circuit layout
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Paper Abstract

We demonstrate a consolidated metric that can quantitatively express design quality with respect to multiple yield loss mechanisms. Using this metric and the design analysis and optimization framework we have developed, we study the effectiveness of different layout enhancements and the effect of combining multiple enhancements in a single layout. Previous works attempted to select a single combination of design enhancements that presents the optimal trade-off between different yield loss mechanisms and optimizes the total yield. We show that the optimal solution depends on the layout features on a small scale, thus the best yield can be achieved by selecting different combinations of enhancements in different locations. We introduce a general form of the cost function and compare different layout configurations, taking into account lithography process variations, random defect distributions, and recommended design rules. Since all layout configurations represent the same electrical devices, it is possible to dynamically determine the most robust layout implementation according to the cost function that incorporates the relative importance of each yield loss contributor. We compare the globally optimized layout, where the sequence of yield enhancements is selected based on the overall design yield, with locally optimized layouts, where the enhancements are fine-tuned for each location. We show that when comparing different layout enhancements it is important to consider two types of yield tradeoffs, local tradeoffs where the same layout feature impacts several yield loss mechanisms, and global tradeoffs where the net effect of a particular type of layout enhancement depends on its location. By selectively applying yield enhancements to the areas of the layout where they are needed we can considerably improve the overall design quality.

Paper Details

Date Published: 30 October 2007
PDF: 12 pages
Proc. SPIE 6730, Photomask Technology 2007, 67300Y (30 October 2007); doi: 10.1117/12.746722
Show Author Affiliations
Fedor G. Pikus, Mentor Graphics Corp. (United States)
J. Andres Torres, Mentor Graphics Corp. (United States)

Published in SPIE Proceedings Vol. 6730:
Photomask Technology 2007
Robert J. Naber; Hiroichi Kawahira, Editor(s)

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