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Proceedings Paper

Study of impacts of mask structure on hole pattern in EUVL
Author(s): Nobuyuki Iriki; Yukiyasu Arisawa; Hajime Aoyama; Toshihiko Tanaka
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Paper Abstract

In this paper we focus exclusively on hole process. The motivation here is to investigate on the performance of EUVL for hole patterning in relation to contributions from mask, exposure tool, and resist process. For this purpose we use a waveguide simulation package that is capable of computing 3-D mask structure at very fast speed. We investigated the patterning characteristics of arrayed holes influenced by mask structure that involve absorber thickness and sidewall angle. Regarding the absorber thickness, we found in our preliminary process window evaluation that thinner absorber mask requires lower dose than thick absorber mask does. As lowering of dose is important for the development of cost effective EUVL technology, we have intensively investigated impacts of thin mask on printability. As it turned out that thin absorber mask evaluated in this paper required not only reduced dose but also exhibited improved process window. At the same time we confirmed that top CD of mask pattern is sensitive to required dose even though bottom reflection area of hole pattern happen to remain constant. The contributing parameters in shaping the side wall are top CD, bottom CD, and thickness of the absorber. In this paper we studied the combined behavior of these parameters that we call 3-D mask error impact. In Selete infrastructure, the technologies of EUVL for realizing full field exposure system are developed using a small field exposure tool (SFET). Using this tool, experimental hole formation was carried out. We also introduce simulations based on experiments.

Paper Details

Date Published: 30 October 2007
PDF: 10 pages
Proc. SPIE 6730, Photomask Technology 2007, 67305K (30 October 2007); doi: 10.1117/12.746592
Show Author Affiliations
Nobuyuki Iriki, Semiconductor Leading Edge Technologies Inc. (Japan)
Yukiyasu Arisawa, Semiconductor Leading Edge Technologies Inc. (Japan)
Hajime Aoyama, Semiconductor Leading Edge Technologies Inc. (Japan)
Toshihiko Tanaka, Semiconductor Leading Edge Technologies Inc. (Japan)


Published in SPIE Proceedings Vol. 6730:
Photomask Technology 2007
Robert J. Naber; Hiroichi Kawahira, Editor(s)

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