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Proceedings Paper

A hardware design on node in transport MPLS packet network based on FPGA
Author(s): Wu Jia; Zhicheng Li; Zhihui Zhang; Juntao Liu; Xiaofei Li; Jialiang Zhang; Yongjun Zhang; Wanyi Gu
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Paper Abstract

It Researches key technologies and hardware node structure of the Transport MPLS packet network. Main technology is super high speed FPGA. The transport plane adapts the layer 3 service signals from client equipments and forwards them. There are two types of node in transport plane, edge node (EN) or core node (CN), and the nodes realized with large-scale FPGA chip have three main function units and six types of board. The EN adapts the layer 3 service signals such as TDM, Packet and Cell to TM signals by add shim. The CN is responsible for the TM signals switching in higher speed than traditional packet network such as Ethernet. Control plane is embedded in a FPGA chip and designed based on the ASON core technique (GMPLS) such as the transport label switching path (T-LSP) maintaining (set up, release, state monitoring), route controlling and protect recovering and so on.

Paper Details

Date Published: 19 November 2007
PDF: 6 pages
Proc. SPIE 6784, Network Architectures, Management, and Applications V, 678425 (19 November 2007); doi: 10.1117/12.746121
Show Author Affiliations
Wu Jia, Beijing Univ. of Posts and Telecommunications (China)
Zhicheng Li, Beijing Univ. of Posts and Telecommunications (China)
Zhihui Zhang, Beijing Univ. of Posts and Telecommunications (China)
Juntao Liu, Beijing Univ. of Posts and Telecommunications (China)
Xiaofei Li, Beijing Univ. of Posts and Telecommunications (China)
Jialiang Zhang, Beijing Univ. of Posts and Telecommunications (China)
Yongjun Zhang, Beijing Univ. of Posts and Telecommunications (China)
Wanyi Gu, Beijing Univ. of Posts and Telecommunications (China)


Published in SPIE Proceedings Vol. 6784:
Network Architectures, Management, and Applications V
Jianli Wang; Gee-Kung Chang; Yoshio Itaya; Herwig Zech, Editor(s)

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