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Proceedings Paper

Paving the way to a full chip gate level double patterning application
Author(s): Henning Haffner; Jason Meiring; Zachary Baum; Scott Halle
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Paper Abstract

Double patterning lithography processes can offer significant yield enhancement for challenging circuit designs. Many decomposition (i.e. the process of dividing the layout design into first and second exposures) techniques are possible, but the focus of this paper is on the use of a secondary "cut" mask to trim away extraneous features left from the first exposure. This approach has the advantage that each exposure only needs to support a subset of critical features (e.g. dense lines with the first exposure, isolated spaces with the second one). The extraneous features ("printing assist features" or PrAFs) are designed to support the process window of critical features much like the role of the subresolution assist features (SRAFs) in conventional processes. However, the printing nature of PrAFs leads to many more design options, and hence a greater process and decomposition parameter exploration space, than are available for SRAFs. A decomposition scheme using PRAFs was developed for a gate level process. A critical driver of the work was to deliver improved across-chip linewidth variation (ACLV) performance versus an optimized single exposure process while providing support for a larger range of critical features. A variety of PRAF techniques were investigated by simulation, with a PrAF scheme similar to standard SRAF rules being chosen as the optimal solution [1]. This paper discusses aspects of the code development for an automated PrAF generation and placement scheme and the subsequent decomposition of a layout into two mask levels. While PrAF placement and decomposition is straightforward for layouts with pitch and orientation restrictions, it becomes rather complex for unrestricted layout styles. Because this higher complexity yields more irregularly shaped PrAFs, mask making becomes another critical driver of the optimum placement and clean-up strategies. Examples are given of how those challenges are met or can be successfully circumvented. During subsequent decomposition of the PrAF-enhanced layout into two independent mask levels, various geometric decomposition parameters have to be considered. As an example, the removal of PrAFs has to be guaranteed by a minimum required overlap of the cut mask opening past any PrAF edge. It is discussed that process assumptions such as CD tolerances and overlay as well as inter-level relationship ground rules need to be considered to successfully optimize the final decomposition scheme. Furthermore, simulation and experimental results regarding not only ACLV but also across-device linewidth variation (ADLV) are analyzed.

Paper Details

Date Published: 30 October 2007
PDF: 12 pages
Proc. SPIE 6730, Photomask Technology 2007, 67302C (30 October 2007); doi: 10.1117/12.746116
Show Author Affiliations
Henning Haffner, Infineon Technologies NA Corp. (United States)
Jason Meiring, IBM Semiconductor Research and Development Ctr. (United States)
Zachary Baum, IBM Semiconductor Research and Development Ctr. (United States)
Scott Halle, IBM Semiconductor Research and Development Ctr. (United States)


Published in SPIE Proceedings Vol. 6730:
Photomask Technology 2007
Robert J. Naber; Hiroichi Kawahira, Editor(s)

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