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Proceedings Paper

Fault tolerant techniques for integrated circuits in submicron and nanotechnologies
Author(s): Angelica Bacivarov
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Paper Abstract

Drastic device shrinking, power supply reduction, and increasing operating speeds that accompany the technological evolution to deeper submicron, reduce significantly the noise margins and thus the reliability of deep submicron ICs. A more significant problem is related to the single-event upsets (SEUs). It is predicted that neutrons produced by the sun activity will affect dramatically the operation of future Integrated Circuits (Ics). Self-test and fault tolerance in submicron and nanotechnologies becoming hitherto imperative. Perhaps the most significant problem concerns the sensitivity of future IC generations face to various noise sources, and in particularly face to energetic particles. This paper analyses some of designing soft-error tolerant circuits.

Paper Details

Date Published: 31 May 2007
PDF: 7 pages
Proc. SPIE 6635, Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies III, 66350B (31 May 2007); doi: 10.1117/12.741873
Show Author Affiliations
Angelica Bacivarov, EUROQUALROM, Univ. Politehnica Bucharest (Romania)

Published in SPIE Proceedings Vol. 6635:
Advanced Topics in Optoelectronics, Microelectronics, and Nanotechnologies III

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