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Proceedings Paper

Realization and application of a 111 million pixel backside-illuminated detector and camera
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Paper Abstract

A full-wafer, 10,580 × 10,560 pixel (95 × 95 mm) CCD was designed and tested at Semiconductor Technology Associates (STA) with 9 μm square pixels and 16 outputs. The chip was successfully fabricated in 2006 at DALSA and some performance results are presented here. This program was funded by the Office of Naval Research through a Small Business Innovation in Research (SBIR) program requested by the U.S. Naval Observatory for its next generation astrometric sky survey programs. Using Leach electronics, low read-noise output of the 111 million pixels requires 16 seconds at 0.9 MHz. Alternative electronics developed at STA allow readout at 20 MHz. Some modifications of the design to include anti-blooming features, a larger number of outputs, and use of p-channel material for space applications are discussed.

Paper Details

Date Published: 17 September 2007
PDF: 8 pages
Proc. SPIE 6690, Focal Plane Arrays for Space Telescopes III, 669008 (17 September 2007); doi: 10.1117/12.736961
Show Author Affiliations
Norbert Zacharias, U.S. Naval Observatory (United States)
Bryan Dorland, U.S. Naval Observatory (United States)
Richard Bredthauer, Semiconductor Technology Associates (United States)
Kasey Boggs, Semiconductor Technology Associates (United States)
Greg Bredthauer, Semiconductor Technology Associates (United States)
Mike Lesser, Steward Observatory, Univ. of Arizona (United States)


Published in SPIE Proceedings Vol. 6690:
Focal Plane Arrays for Space Telescopes III
Thomas J. Grycewicz; Cheryl J. Marshall; Penny G. Warren, Editor(s)

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