Today's semiconductors consist of up to forty structured layers which make up the electric circuit. Since the market demands more powerful chips at minimal cost, the structure size is decreased with every technology node. The smaller the features become, the more sensitive is the functional effciency of the chip with respect to placement errors. One crucial component for placement errors is the mask which can be viewed as a blueprint of the layer's structures. Hence, placement accuracy requirements for masks are also tightening rapidly. These days, mask shops strive for improving their positioning performance. However, more and more effort is required which will increase the costs for masks. Therefore, the transfer of mask placement errors onto the wafer is analyzed in order to check the guidelines which are used for deriving placement error specifications. In the first section of this paper the basic concepts for measuring placement errors are provided. Then, a method is proposed which is able to characterize the transfer of placement errors from mask to wafer. This is followed by two sections giving a thorough statistical analysis of this method. In the fifth section, the connection to placement accuracy specifications on mask and wafer is established. Finally, the method is applied to a set of test masks provided by AMTC and printed by AMD.

Date Published: 3 May 2007
PDF: 10 pages
Proc. SPIE 6533, 23rd European Mask and Lithography Conference, 65330U (3 May 2007); doi: 10.1117/12.736958

Published in SPIE Proceedings Vol. 6533:
23rd European Mask and Lithography Conference
Uwe F. W. Behringer, Editor(s)