Share Email Print

Proceedings Paper

OPC structures for maskshops qualification for the CMOS65nm and CMOS45nm nodes
Author(s): Frank Sundermann; Yorick Trouiller; Jean-Christophe Urbani; Christophe Couderc; Jérôme Belledent; Amandine Borjon; Franck Foussadier; Christian Gardin; Laurent LeCam; Yves Rody; Mazen Saied; Emek Yesilada; Catherine Martinelli; Bill Wilkinson; Florent Vautrin; Nicolo Morgana; Frederic Robert; Patrick Montgomery; Gurwan Kerrien; Jonathan Planchot; Vincent Farys; Jean-Luc Di Maria
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Several qualification stages are required for new maskshop tools, first step is done by the maskshop internally. Taking a new writer for example, the maskshop will review the basic factory and site acceptance tests, including CD uniformity, CD linearity, local CD errors and registration errors. The second step is to have dedicated OPC (Optical Proximity Correction) structures from the wafer fab. These dedicated OPC structures will be measured by the maskshop to get a reticle CD metrology trend line. With this trend line, we can: - ensure the stability at reticle level of the maskshop processes - put in place a matching procedure to guarantee the same OPC signature at reticle level in case of any internal maskshop process change or new maskshop evaluation. Changes that require qualification could be process changes for capacity reasons, like introducing a new writer or a new manufacturing line, or for capability reasons, like a new process (new developer tool for example) introduction. Most advanced levels will have dedicated OPC structures. Also dedicated maskshop processes will be monitored with these specific OPC structures. In this paper, we will follow in detail the different reticle CD measurements of dedicated OPC structures for the three advanced logic levels of the 65nm node: poly level, contact level and metal level. The related maskshop's processes are - for poly: eaPSM 193nm with a nega CAR (Chemically Amplified Resist) process for Clear Field L/S (Lines & Space) reticles - for contact: eaPSM 193nm with a posi CAR process for Dark Field Holes reticles - for metal1: eaPSM 193nm with a posi CAR process for Dark Field L/S reticles. For all these structures, CD linearity, CD through pitch, length effects, and pattern density effects will be monitored. To average the metrology errors, the structures are placed twice on the reticle. The first part of this paper will describe the different OPC structures. These OPC structures are close to the DRM (Design Rule Manual) of the dedicated levels to be monitored. The second part of the paper will describe the matching procedure to ensure the same OPC signature at reticle level. We will give an example of an internal maskshop matching exercise, which could be needed when we switched from an already qualified 50 KeV tool to a new 50 KeV tool. The second example is the same matching exercise of our 65nm OPC structures, but with two different maskshops. The last part of the paper will show first results on dedicated OPC structures for the 45nm node.

Paper Details

Date Published: 3 May 2007
PDF: 13 pages
Proc. SPIE 6533, 23rd European Mask and Lithography Conference, 65330E (3 May 2007); doi: 10.1117/12.736927
Show Author Affiliations
Frank Sundermann, STMicroelectronics (France)
Yorick Trouiller, LETI-CEA (France)
Jean-Christophe Urbani, STMicroelectronics (France)
Christophe Couderc, NXP Semiconductors (France)
Jérôme Belledent, NXP Semiconductors (France)
Amandine Borjon, NXP Semiconductors (France)
Franck Foussadier, STMicroelectronics (France)
Christian Gardin, Freescale Semiconductor, Inc. (France)
Laurent LeCam, NXP Semiconductors (France)
Yves Rody, NXP Semiconductors (France)
Mazen Saied, Freescale Semiconductor, Inc. (France)
Emek Yesilada, Freescale Semiconductor, Inc. (France)
Catherine Martinelli, STMicroelectronics (France)
Bill Wilkinson, Freescale Semiconductor, Inc. (France)
Florent Vautrin, STMicroelectronics (France)
Nicolo Morgana, Freescale Semiconductor, Inc. (France)
Frederic Robert, STMicroelectronics (France)
Patrick Montgomery, Freescale Semiconductor, Inc. (France)
Gurwan Kerrien, STMicroelectronics (France)
Jonathan Planchot, STMicroelectronics (France)
Vincent Farys, STMicroelectronics (France)
Jean-Luc Di Maria, LETI-CEA (France)

Published in SPIE Proceedings Vol. 6533:
23rd European Mask and Lithography Conference
Uwe F. W. Behringer, Editor(s)

© SPIE. Terms of Use
Back to Top