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Proceedings Paper

ISA extensions for high-radix online floating-point addition
Author(s): Pouya Dormiani; Miloš D. Ercegovac; O. Colavin
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Paper Abstract

ISA extensions for DLX type architectures are proposed to perform high radix online floating point addition on fixed point units with extended feature sets. Online arithmetic allows most significant digit first computation of results, allowing overlapped execution of dependent operations and offers greater instruction scheduling opportunities than software implementations of conventional floating point addition. In this paper we seek an ISA formulation to find a middle ground between full hardware floating point addition units and software implementations strictly based on available ALU logic.

Paper Details

Date Published: 21 September 2007
PDF: 12 pages
Proc. SPIE 6697, Advanced Signal Processing Algorithms, Architectures, and Implementations XVII, 66970T (21 September 2007); doi: 10.1117/12.734916
Show Author Affiliations
Pouya Dormiani, Univ. of California, Los Angeles (United States)
Miloš D. Ercegovac, Univ. of California, Los Angeles (United States)
O. Colavin, ST Microelectronics Lab. (United States)


Published in SPIE Proceedings Vol. 6697:
Advanced Signal Processing Algorithms, Architectures, and Implementations XVII
Franklin T. Luk, Editor(s)

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