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Proceedings Paper

LDPC decoder with a limited-precision FPGA-based floating-point multiplication coprocessor
Author(s): Raymond Moberly; Michael O'Sullivan; Khurram Waheed
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Paper Abstract

Implementing the sum-product algorithm, in an FPGA with an embedded processor, invites us to consider a tradeoff between computational precision and computational speed. The algorithm, known outside of the signal processing community as Pearl's belief propagation, is used for iterative soft-decision decoding of LDPC codes. We determined the feasibility of a coprocessor that will perform product computations. Our FPGA-based coprocessor (design) performs computer algebra with significantly less precision than the standard (e.g. integer, floating-point) operations of general purpose processors. Using synthesis, targeting a 3,168 LUT Xilinx FPGA, we show that key components of a decoder are feasible and that the full single-precision decoder could be constructed using a larger part. Soft-decision decoding by the iterative belief propagation algorithm is impacted both positively and negatively by a reduction in the precision of the computation. Reducing precision reduces the coding gain, but the limited-precision computation can operate faster. A proposed solution offers custom logic to perform computations with less precision, yet uses the floating-point format to interface with the software. Simulation results show the achievable coding gain. Synthesis results help theorize the the full capacity and performance of an FPGA-based coprocessor.

Paper Details

Date Published: 21 September 2007
PDF: 12 pages
Proc. SPIE 6697, Advanced Signal Processing Algorithms, Architectures, and Implementations XVII, 66970R (21 September 2007); doi: 10.1117/12.733510
Show Author Affiliations
Raymond Moberly, San Diego State Univ. (United States)
Michael O'Sullivan, San Diego State Univ. (United States)
Khurram Waheed, San Diego State Univ. (United States)


Published in SPIE Proceedings Vol. 6697:
Advanced Signal Processing Algorithms, Architectures, and Implementations XVII
Franklin T. Luk, Editor(s)

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