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Proceedings Paper

Progress on EUV mask fabrication for 32-nm technology node and beyond
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Paper Abstract

Extreme ultraviolet lithography (EUVL) tool development achieved a big milestone last year as two full-field Alpha Demo Tools (ADT) were shipped to customers by ASML. In the future horizon, a full field "EUV1" exposure tool from Nikon will be available by the end of 20071 and the pre-production EUV exposure tools from ASML are targeted for 20092. It is essential that high quality EUVL masks can be made and delivered to the EUVL tool users to support the technology development. In the past year, we have demonstrated mask fabrication with low stress absorber deposition and good etch process control yielding a vertical etch profile and a mask CD control of 5.7 nm for 32 nm (1x) space and 7.4 nm for 32 nm (1x) lines. Mask pattern resolution of 15 nm (1x) dense lines was achieved. Full field reflective mask die-to-die inspection at a 125nm pixel size was demonstrated after low defect multilayer blanks became available. In this paper, we will present details of the Intel EUVL Mask Pilot Line progress in EUVL mask defect reduction, pattern CD performance, program defect mask design and inspection, in-house absorber film development and its performance, and EUVL metrology tool development. We will demonstrate an overall improvement in EUV mask manufacturing readiness due to our Pilot Line activities.

Paper Details

Date Published: 29 May 2007
PDF: 11 pages
Proc. SPIE 6607, Photomask and Next-Generation Lithography Mask Technology XIV, 66070R (29 May 2007); doi: 10.1117/12.728941
Show Author Affiliations
Guojing Zhang, Intel Corp. (United States)
Pei-Yang Yan, Intel Corp. (United States)
Ted Liang, Intel Corp. (United States)
Seh-jin Park, Intel Corp. (United States)
Peter Sanchez, Intel Corp. (United States)
Emily Y. Shu, Intel Corp. (United States)
Erdem A Ultanir, Intel Corp. (United States)
Sven Henrichs, Intel Corp. (United States)
Alan Stivers, Intel Corp. (United States)
Gilroy Vandentop, Intel Corp. (United States)
Barry Lieberman, Intel Corp. (United States)
Ping Qu, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 6607:
Photomask and Next-Generation Lithography Mask Technology XIV
Hidehiro Watanabe, Editor(s)

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