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Proceedings Paper

Characterization and system modeling of a 5-Mpixel CMOS array
Author(s): Kirsten Cabanas-Holmen; David Dorn; Curtis Tesdahl
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Paper Abstract

We present characterization results for a 5 million pixel CMOS image sensor designed for high speed applications. This sensor is capable of outputting 14 frames per second and incorporates on-chip 12-bit digitization. We present measurements of system gain, read noise, dark current, charge capacity, linearity, photo response non-uniformity, defects, and quantum efficiency. The image sensor incorporates exposure control functionality, windowing, on-chip binning, anti-blooming capability and rolling shutter architecture to implement image capture mode. The results show a favorable aspect of the ability to achieve high speed, high resolution, and very good sensitivity in a monolithic CMOS sensor. Architecture trades for high speed imaging systems utilizing CCDs and CMOS sensors are also presented.

Paper Details

Date Published: 21 February 2007
PDF: 10 pages
Proc. SPIE 6501, Sensors, Cameras, and Systems for Scientific/Industrial Applications VIII, 65010Q (21 February 2007); doi: 10.1117/12.726364
Show Author Affiliations
Kirsten Cabanas-Holmen, Pelco (United States)
David Dorn, Pelco (United States)
Curtis Tesdahl, Pelco (United States)

Published in SPIE Proceedings Vol. 6501:
Sensors, Cameras, and Systems for Scientific/Industrial Applications VIII
Morley M. Blouke, Editor(s)

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