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Proceedings Paper

A methodology for switching noise estimation at gate level
Author(s): Javier Castro; Pilar Parra; Antonio J. Acosta
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Paper Abstract

This paper provides a simple methodology, based on available CAD tools, able of extracting valuable information on supply current curves, otherwise limited by the layout disposal, making it impracticable for the present high density circuits. The approach starts at HDL level, which will be automatically synthesized to a gate level being the peak power (one peak per clock cycle) measured at this level, giving an idea of the switching noise generated. Although an indirect method, it provides a quantitative value of noise valid for comparison between different proposals. To assess the methodology two different tools are used: PrimePower and NanoSim, both from Synopsys, that generate an average power and a peak power value. We will see that NanoSim is good for noise estimation but this is not the case of PrimePower.

Paper Details

Date Published: 23 May 2007
PDF: 8 pages
Proc. SPIE 6590, VLSI Circuits and Systems III, 65900U (23 May 2007); doi: 10.1117/12.724164
Show Author Affiliations
Javier Castro, Instituto de Microelectrónica de Sevilla-CNM-CSIC/Univ. de Sevilla (Spain)
Pilar Parra, Instituto de Microelectrónica de Sevilla-CNM-CSIC/Univ. de Sevilla (Spain)
Antonio J. Acosta, Instituto de Microelectrónica de Sevilla-CNM-CSIC/Univ. de Sevilla (Spain)


Published in SPIE Proceedings Vol. 6590:
VLSI Circuits and Systems III
Valentín de Armas Sosa; Kamran Eshraghian; Félix B. Tobajas, Editor(s)

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