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Proceedings Paper

Address-event-based platform for bioinspired spiking systems
Author(s): A. Jiménez-Fernández; C. D. Luján; A. Linares-Barranco; F. Gómez-Rodríguez; M. Rivas; G. Jiménez; A. Civit
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Paper Abstract

Address Event Representation (AER) is an emergent neuromorphic interchip communication protocol that allows a real-time virtual massive connectivity between huge number neurons, located on different chips. By exploiting high speed digital communication circuits (with nano-seconds timings), synaptic neural connections can be time multiplexed, while neural activity signals (with mili-seconds timings) are sampled at low frequencies. Also, neurons generate "events" according to their activity levels. More active neurons generate more events per unit time, and access the interchip communication channel more frequently, while neurons with low activity consume less communication bandwidth. When building multi-chip muti-layered AER systems, it is absolutely necessary to have a computer interface that allows (a) reading AER interchip traffic into the computer and visualizing it on the screen, and (b) converting conventional frame-based video stream in the computer into AER and injecting it at some point of the AER structure. This is necessary for test and debugging of complex AER systems. In the other hand, the use of a commercial personal computer implies to depend on software tools and operating systems that can make the system slower and un-robust. This paper addresses the problem of communicating several AER based chips to compose a powerful processing system. The problem was discussed in the Neuromorphic Engineering Workshop of 2006. The platform is based basically on an embedded computer, a powerful FPGA and serial links, to make the system faster and be stand alone (independent from a PC). A new platform is presented that allow to connect up to eight AER based chips to a Spartan 3 4000 FPGA. The FPGA is responsible of the network communication based in Address-Event and, at the same time, to map and transform the address space of the traffic to implement a pre-processing. A MMU microprocessor (Intel XScale 400MHz Gumstix Connex computer) is also connected to the FPGA to allow the platform to implement eventbased algorithms to interact to the AER system, like control algorithms, network connectivity, USB support, etc. The LVDS transceiver allows a bandwidth of up to 1.32 Gbps, around ~66 Mega events per second (Mevps).

Paper Details

Date Published: 22 May 2007
PDF: 10 pages
Proc. SPIE 6592, Bioengineered and Bioinspired Systems III, 659206 (22 May 2007); doi: 10.1117/12.724156
Show Author Affiliations
A. Jiménez-Fernández, Univ. de Sevilla (Spain)
C. D. Luján, Univ. de Sevilla (Spain)
A. Linares-Barranco, Univ. de Sevilla (Spain)
F. Gómez-Rodríguez, Univ. de Sevilla (Spain)
M. Rivas, Univ. de Sevilla (Spain)
G. Jiménez, Univ. de Sevilla (Spain)
A. Civit, Univ. de Sevilla (Spain)


Published in SPIE Proceedings Vol. 6592:
Bioengineered and Bioinspired Systems III
Paolo Arena; Ángel Rodríguez-Vázquez; Gustavo Liñán-Cembrano, Editor(s)

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