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Proceedings Paper

MPEG-4 ASP SoC receiver with novel image enhancement techniques for DAB networks
Author(s): D. Barreto; A. Quintana; L. García; G. M. Callicó; A. Núñez
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Paper Abstract

This paper presents a system for real-time video reception in low-power mobile devices using Digital Audio Broadcast (DAB) technology for transmission. A demo receiver terminal is designed into a FPGA platform using the Advanced Simple Profile (ASP) MPEG-4 standard for video decoding. In order to keep the demanding DAB requirements, the bandwidth of the encoded sequence must be drastically reduced. In this sense, prior to the MPEG-4 coding stage, a pre-processing stage is performed. It is firstly composed by a segmentation phase according to motion and texture based on the Principal Component Analysis (PCA) of the input video sequence, and secondly by a down-sampling phase, which depends on the segmentation results. As a result of the segmentation task, a set of texture and motion maps are obtained. These motion and texture maps are also included into the bit-stream as user data side-information and are therefore known to the receiver. For all bit-rates, the whole encoder/decoder system proposed in this paper exhibits higher image visual quality than the alternative encoding/decoding method, assuming equal image sizes. A complete analysis of both techniques has also been performed to provide the optimum motion and texture maps for the global system, which has been finally validated for a variety of video sequences. Additionally, an optimal HW/SW partition for the MPEG-4 decoder has been studied and implemented over a Programmable Logic Device with an embedded ARM9 processor. Simulation results show that a throughput of 15 QCIF frames per second can be achieved with low area and low power implementation.

Paper Details

Date Published: 10 May 2007
PDF: 11 pages
Proc. SPIE 6590, VLSI Circuits and Systems III, 659009 (10 May 2007); doi: 10.1117/12.723740
Show Author Affiliations
D. Barreto, Univ. de Las Palmas de Gran Canaria (Spain)
A. Quintana, Univ. de Las Palmas de Gran Canaria (Spain)
L. García, Univ. de Las Palmas de Gran Canaria (Spain)
G. M. Callicó, Univ. de Las Palmas de Gran Canaria (Spain)
A. Núñez, Univ. de Las Palmas de Gran Canaria (Spain)

Published in SPIE Proceedings Vol. 6590:
VLSI Circuits and Systems III
Valentín de Armas Sosa; Kamran Eshraghian; Félix B. Tobajas, Editor(s)

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