Share Email Print

Proceedings Paper

Automatic logic synthesis for parallel alternating latches clocking schemes
Author(s): D. Guerrero; M. Bellido; J. Juan; A. Millan; P. Ruiz; E. Ostua; J. Viejo
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

This paper proposes a VHDL coding technique that allows for the automatic synthesis of digital circuits using the so called Parallel Alternating Latches Clocking Schemes (PALACS). The proposed method greatly improves the applicability of PALACS and its benefits. This technique is verified through design examples in three different CMOS processes and using logic level simulation, with successful results in all the cases.

Paper Details

Date Published: 10 May 2007
PDF: 9 pages
Proc. SPIE 6590, VLSI Circuits and Systems III, 659006 (10 May 2007); doi: 10.1117/12.723664
Show Author Affiliations
D. Guerrero, Univ. of Seville (Spain)
M. Bellido, Univ. of Seville (Spain)
J. Juan, Univ. of Seville (Spain)
A. Millan, Univ. of Seville (Spain)
P. Ruiz, Univ. of Seville (Spain)
E. Ostua, Univ. of Seville (Spain)
J. Viejo, Univ. of Seville (Spain)

Published in SPIE Proceedings Vol. 6590:
VLSI Circuits and Systems III
Valentín de Armas Sosa; Kamran Eshraghian; Félix B. Tobajas, Editor(s)

© SPIE. Terms of Use
Back to Top