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Proceedings Paper

Design flow for implementing image processing in FPGAs
Author(s): M. Trakalo; G. Giles
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Paper Abstract

A design flow for implementing a dynamic gamma algorithm in an FPGA is described. Real-time video processing makes enormous demands on processing resources. An FPGA solution offers some advantages over commercial video chip and DSP implementation alternatives. The traditional approach to FPGA development involves a system engineer designing, modeling and verifying an algorithm and writing a specification. A hardware engineer uses the specification as a basis for coding in VHDL and testing the algorithm in the FPGA with supporting electronics. This process is work intensive and the verification of the image processing algorithm executing on the FPGA does not occur until late in the program. The described design process allows the system engineer to design and verify a true VHDL version of the algorithm, executing in an FPGA. This process yields reduced risk and development time. The process is achieved by using Xilinx System Generator in conjunction with Simulink® from The MathWorks. System Generator is a tool that bridges the gap between the high level modeling environment and the digital world of the FPGA. System Generator is used to develop the dynamic gamma algorithm for the contrast enhancement of a candidate display product. The results of this effort are to increase the dynamic range of the displayed video, resulting in a more useful image for the user.

Paper Details

Date Published: 26 April 2007
PDF: 10 pages
Proc. SPIE 6558, Display Technologies and Applications for Defense, Security, and Avionics, 65580C (26 April 2007); doi: 10.1117/12.722511
Show Author Affiliations
M. Trakalo, General Dynamics Canada (Canada)
G. Giles, General Dynamics Canada (Canada)

Published in SPIE Proceedings Vol. 6558:
Display Technologies and Applications for Defense, Security, and Avionics
John T. Thomas; Andrew Malloy, Editor(s)

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