Share Email Print
cover

Proceedings Paper

Mixed signal SystemC modelling of a SoC architecture with Dynamic Voltage Scaling
Author(s): G. Leoce; R. D'Aparo; G. B. Vece; G. Biagetti; S. Orcioni; M. Conti
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Dynamic Voltage Scaling is a technique that reduces supply voltage and clock frequency, depending on system workload, with the aim of reducing power dissipation. This works is devoted to the modelling and integration in the same system level simulation environment of the analog DC-DC converter for Dynamic Voltage Scaling, the Dynamic Power Management and a test System on Chip with three Masters and two Slaves connected to the AMBA AHB bus. The DC-DC converter is described with a detail such that it is possible to verify the effect of the transient during the change of supply voltage on the performance of the DVS algorithm. SystemC and its extension SystemC-WMS have been used as description languages in which a system level description of the dynamic supply management coexists with the analog switching power converter and its control.

Paper Details

Date Published: 10 May 2007
PDF: 11 pages
Proc. SPIE 6590, VLSI Circuits and Systems III, 65901H (10 May 2007); doi: 10.1117/12.722072
Show Author Affiliations
G. Leoce, Univ. Politecnica delle Marche (Italy)
R. D'Aparo, Univ. Politecnica delle Marche (Italy)
G. B. Vece, Univ. Politecnica delle Marche (Italy)
G. Biagetti, Univ. Politecnica delle Marche (Italy)
S. Orcioni, Univ. Politecnica delle Marche (Italy)
M. Conti, Univ. Politecnica delle Marche (Italy)


Published in SPIE Proceedings Vol. 6590:
VLSI Circuits and Systems III
Valentín de Armas Sosa; Kamran Eshraghian; Félix B. Tobajas, Editor(s)

© SPIE. Terms of Use
Back to Top