Share Email Print

Proceedings Paper

Toward the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture
Author(s): S. López; A. Kanstein; J. F. López; M. Berekovic; R. Sarmiento; J.-Y. Mignolet
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

The decoding of a H.264/AVC bitstream represents a complex and time-consuming task. Due to this reason, efficient implementations in terms of performance and flexibility are mandatory for real time applications. In this sense, the mapping of the motion compensation and deblocking filtering stages onto a coarse-grained reconfigurable architecture named ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is presented in this paper. The results obtained show a considerable reduction in the number of cycles and memory accesses needed to perform the motion compensation as well as an increase in the degree of parallelism when compared with an implementation on a Very Long Instruction Word (VLIW) dedicated processor.

Paper Details

Date Published: 10 May 2007
PDF: 10 pages
Proc. SPIE 6590, VLSI Circuits and Systems III, 65900A (10 May 2007); doi: 10.1117/12.722042
Show Author Affiliations
S. López, Univ. of Las Palmas de Gran Canaria (Spain)
A. Kanstein, Freescale, Inc. (France)
J. F. López, Univ. of Las Palmas de Gran Canaria (Spain)
M. Berekovic, IMEC (Belgium)
R. Sarmiento, Univ. of Las Palmas de Gran Canaria (Spain)
J.-Y. Mignolet, IMEC (Belgium)

Published in SPIE Proceedings Vol. 6590:
VLSI Circuits and Systems III
Valentín de Armas Sosa; Kamran Eshraghian; Félix B. Tobajas, Editor(s)

© SPIE. Terms of Use
Back to Top