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Proceedings Paper

Variable length packet scheduler algorithm with QoS support
Author(s): R. Arteaga; F. Tobajas; R. Esper-Chaín; M. A. Monzón; R. Regidor; V. De Armas; R. Sarmiento
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Paper Abstract

A novel variable length packet scheduling algorithm focused on real output queue reference architecture is presented in this paper. The main features of this packet scheduler development are the Quality of Service (QoS) and variable length packet support. The packet scheduler supports up to eight traffic classes which can be assigned up to two different priorities. The bandwidth assigned to any traffic class is configurable. The packet scheduler has been described and simulated in C++ language under uniform and bursty traffic conditions.

Paper Details

Date Published: 10 May 2007
PDF: 11 pages
Proc. SPIE 6590, VLSI Circuits and Systems III, 659012 (10 May 2007); doi: 10.1117/12.721947
Show Author Affiliations
R. Arteaga, Univ. of Las Palmas de Gran Canaria (Spain)
F. Tobajas, Univ. of Las Palmas de Gran Canaria (Spain)
R. Esper-Chaín, Univ. of Las Palmas de Gran Canaria (Spain)
M. A. Monzón, Univ. of Las Palmas de Gran Canaria (Spain)
R. Regidor, Univ. of Las Palmas de Gran Canaria (Spain)
V. De Armas, Univ. of Las Palmas de Gran Canaria (Spain)
R. Sarmiento, Univ. of Las Palmas de Gran Canaria (Spain)


Published in SPIE Proceedings Vol. 6590:
VLSI Circuits and Systems III
Valentín de Armas Sosa; Kamran Eshraghian; Félix B. Tobajas, Editor(s)

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