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Proceedings Paper

Implementation of a parametrizable router architecture for networks-on-chip (NoC) with quality of service (QoS) support
Author(s): R. Regidor; F. Tobajas; V. De Armas; J. M. Rivero; R. Sarmiento
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Paper Abstract

Managing the complexity of designing Systems-on-Chip (SoC) containing billions of transistors requires decoupling computation from communication. Networks-on-Chip (NoC) have been proposed as a solution for managing this problem as they meet the reusability, scalability and parallelism requirements of these systems, while coping with power constraints and clock distribution. In this paper, the implementation of a router's architecture for NoC with both guaranteed and best-effort services support is described, and some synthesis results are presented. The proposed router architecture is parameterized on the number of virtual channels, the size of virtual channels, the number of virtual channels for guaranteed traffic, the relative priority of the guaranteed traffic, and the switching technique.

Paper Details

Date Published: 10 May 2007
PDF: 10 pages
Proc. SPIE 6590, VLSI Circuits and Systems III, 65901L (10 May 2007); doi: 10.1117/12.721922
Show Author Affiliations
R. Regidor, Univ. of Las Palmas de Gran Canaria (Spain)
F. Tobajas, Univ. of Las Palmas de Gran Canaria (Spain)
V. De Armas, Univ. of Las Palmas de Gran Canaria (Spain)
J. M. Rivero, Univ. of Las Palmas de Gran Canaria (Spain)
R. Sarmiento, Univ. of Las Palmas de Gran Canaria (Spain)

Published in SPIE Proceedings Vol. 6590:
VLSI Circuits and Systems III
Valentín de Armas Sosa; Kamran Eshraghian; Félix B. Tobajas, Editor(s)

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