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Proceedings Paper

A design tool for high-resolution high-frequency cascade continuous-time ΣΔ modulators
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Paper Abstract

This paper introduces a CAD methodology to assist the designer in the implementation of continuous-time (CT) cascade ΣΔ modulators. The salient features of this methodology are: (a) flexible behavioral modeling for optimum accuracy-efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity; and (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology will be illustrated via the design of a 12 bit 20 MHz CT ΣΔ modulator in a 1.2V 130nm CMOS technology.

Paper Details

Date Published: 23 May 2007
PDF: 12 pages
Proc. SPIE 6590, VLSI Circuits and Systems III, 659016 (23 May 2007); doi: 10.1117/12.721896
Show Author Affiliations
R. Tortosa, Instituto de Microelectrónica de Sevilla, CSIC, Univ. de Sevilla (Spain)
R. Castro-López, Instituto de Microelectrónica de Sevilla, CSIC, Univ. de Sevilla (Spain)
J. M. de la Rosa, Instituto de Microelectrónica de Sevilla, CSIC, Univ. de Sevilla (Spain)
A. Rodríguez-Vázquez, Instituto de Microelectrónica de Sevilla, CSIC, Univ. de Sevilla (Spain)
F. V. Fernández, Instituto de Microelectrónica de Sevilla, CSIC, Univ. de Sevilla (Spain)


Published in SPIE Proceedings Vol. 6590:
VLSI Circuits and Systems III
Valentín de Armas Sosa; Kamran Eshraghian; Félix B. Tobajas, Editor(s)

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