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Proceedings Paper

Resizing methodology for CMOS analog circuits
Author(s): Timothée Levi; Jean Tomas; Noëlle Lewis; Pascal Fouillat
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Paper Abstract

This paper proposes a CMOS resizing methodology for analog circuits during a technology migration. The scaling rules aim to be easy to apply and are based on the simplest MOS transistor model. The principle is to transpose one circuit topology from one technology to another, while keeping the main figures of merit, and the issue is to quickly calculate the new transistor dimensions. Furthermore, when the target technology has smaller minimum length, we expect to obtain a decrease of area. This methodology is applied to both linear and non-linear examples: an OTA and a ring oscillator. The results are compared on three CMOS processes whose minimum length is 0.8 μm, 0.35 μm, 0.25 μm.

Paper Details

Date Published: 10 May 2007
PDF: 10 pages
Proc. SPIE 6590, VLSI Circuits and Systems III, 65900W (10 May 2007); doi: 10.1117/12.721871
Show Author Affiliations
Timothée Levi, Univ. Bordeaux I (France)
Jean Tomas, Univ. Bordeaux I (France)
Noëlle Lewis, Univ. Bordeaux I (France)
Pascal Fouillat, Univ. Bordeaux I (France)

Published in SPIE Proceedings Vol. 6590:
VLSI Circuits and Systems III
Valentín de Armas Sosa; Kamran Eshraghian; Félix B. Tobajas, Editor(s)

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