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Proceedings Paper

Design of clock recovery circuits for optical clocking in DSM CMOS
Author(s): Charles Thangaraj; Kevin Stephenson; Tom Chen; Kevin Lear; Abdul Matheen Raza
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Paper Abstract

CMOS technology scaling especially in the sub-100 nm regime has made signaling in long global a challenge, resulting in a need for an improved interconnect technology. Optical signalling is a promising alternative to existing global interconnects and alleviates interconnect bottle-neck. This paper presents a design of a CMOS trans-impedance amplifier (TIA) that is intended for a truly CMOS compatible on-chip optical clock distribution system. This TIA employs replica biasing technique to achieve stability while maximizing its bandwidth and gain. The design was implemented in a 0.35μm CMOS process and is currently under probe testing. The simulation results show that the design achieved a bandwidth of 1GHz and gain of 128dB-Ω. Extensive Monte-Carlo simulations indicate the superior characteristics of stability under a variety of process and environmental variations.

Paper Details

Date Published: 10 May 2007
PDF: 8 pages
Proc. SPIE 6590, VLSI Circuits and Systems III, 65900F (10 May 2007); doi: 10.1117/12.721646
Show Author Affiliations
Charles Thangaraj, Colorado State Univ. (United States)
Kevin Stephenson, Colorado State Univ. (United States)
Tom Chen, Colorado State Univ. (United States)
Kevin Lear, Colorado State Univ. (United States)
Abdul Matheen Raza, Colorado State Univ. (United States)

Published in SPIE Proceedings Vol. 6590:
VLSI Circuits and Systems III
Valentín de Armas Sosa; Kamran Eshraghian; Félix B. Tobajas, Editor(s)

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