Share Email Print
cover

Proceedings Paper

High-level power estimation for digital system
Author(s): Yaseer A. Durrani; Ana Abril; Teresa Riesgo
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

In this paper, we present a high-level power macromodeling technique at register transfer level (RTL). The proposed methodology allows to estimate the power dissipation on digital systems composed of intellectual property (IP) macro-blocks by using the statistical knowledge of their primary inputs. During the power estimation procedure, the sequence of an input stream is generated by using input metrics. Then, a Monte Carlo zero delay simulation is performed and a power dissipation macromodel function is built from power dissipation results. From then on, this macromodel function can be used to estimate power dissipation of the system just by using the statistics of the IPs primary inputs. In our experiments with the test IP system, the average error is 29.63%.

Paper Details

Date Published: 10 May 2007
PDF: 9 pages
Proc. SPIE 6590, VLSI Circuits and Systems III, 659002 (10 May 2007); doi: 10.1117/12.721182
Show Author Affiliations
Yaseer A. Durrani, Univ. Politécnica de Madrid (Spain)
Ana Abril, Univ. Politécnica de Madrid (Spain)
Teresa Riesgo, Univ. Politécnica de Madrid (Spain)


Published in SPIE Proceedings Vol. 6590:
VLSI Circuits and Systems III
Valentín de Armas Sosa; Kamran Eshraghian; Félix B. Tobajas, Editor(s)

© SPIE. Terms of Use
Back to Top