Share Email Print
cover

Proceedings Paper

OASIS: cryogenically optimized resistive arrays and IRSP subsystems for space-background IR simulation
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

SBIR has completed the development of the first lot of OASIS emitter arrays and custom packaging for cryogenic IR scene projection applications. OASIS performance requirements include a maximum MWIR apparent temperature of greater than 600 K, with 10-90% radiance rise time of less than 6.5 ms. Four (4) arrays have been packaged, integrated, tested and delivered. This paper will report on the first measurements taken of the OASIS resistive emitter arrays at both ambient and cryogenic temperatures. This paper will also provide a discussion of the OASIS cryogenic projector/electronics module (Cryo-PEM) design. We will also describe the novel thermal design employed within the array package and Cryo-PEM assemblies, which allows OASIS to produce radiometrically accurate imagery with reduced thermal lag/gradient artifacts compared to legacy Honeywell cryogenic IRSP assemblies. As OASIS supports both analog and digital input, we will discuss the differences between the two modes in terms of system integration, support electronics and overall array performance.

Paper Details

Date Published: 30 April 2007
PDF: 10 pages
Proc. SPIE 6544, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing XII, 654405 (30 April 2007); doi: 10.1117/12.720610
Show Author Affiliations
Jay James, Santa Barbara Infrared, Inc. (United States)
Joe LaVeigne, Santa Barbara Infrared, Inc. (United States)
Jim Oleson, Santa Barbara Infrared, Inc. (United States)
Greg Matis, Santa Barbara Infrared, Inc. (United States)
John Lannon, RTI International (United States)
Scott Goodwin, RTI International (United States)
Alan Huffman, RTI International (United States)
Steve Solomon, Acumen Scientific (United States)
Paul Bryant, Left Coast Consulting (United States)


Published in SPIE Proceedings Vol. 6544:
Technologies for Synthetic Environments: Hardware-in-the-Loop Testing XII
Robert Lee Murrer, Editor(s)

© SPIE. Terms of Use
Back to Top