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Proceedings Paper

Intellectual property protection of IP cores through high-level watermarking
Author(s): E. Castillo; U. Meyer-Baese; A. García; L. Parrilla; A. Lloris
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Paper Abstract

In this paper a watermarking technique for Intellectual Property Protection (IPP) of FPGA-based systems is proposed. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The proposed watermarking technique relies on a procedure that spreads the digital signature in cells of memory structures at Hardware Description Language (HDL) design level, not increasing the area of the system. This signature is preserved through synthesis, placement and routing processes. The technique includes a procedure for signature extraction requiring minimal modifications to the system. Thus, it is possible to detect the ownership rights without interfering the normal operation of the system and providing high invulnerability. To illustrate the properties of the proposed watermarking technique, both protected and unprotected design examples are compared in terms of area and performance. The analysis of the results shows that the area increase is very low while throughput penalization is almost negligible.

Paper Details

Date Published: 9 April 2007
PDF: 9 pages
Proc. SPIE 6576, Independent Component Analyses, Wavelets, Unsupervised Nano-Biomimetic Sensors, and Neural Networks V, 657619 (9 April 2007); doi: 10.1117/12.719202
Show Author Affiliations
E. Castillo, Univ. of Granada (Spain)
U. Meyer-Baese, Florida State Univ. (United States)
A. García, Univ. of Granada (Spain)
L. Parrilla, Univ. of Granada (Spain)
A. Lloris, Univ. of Granada (Spain)


Published in SPIE Proceedings Vol. 6576:
Independent Component Analyses, Wavelets, Unsupervised Nano-Biomimetic Sensors, and Neural Networks V
Harold H. Szu; Jack Agee, Editor(s)

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