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Proceedings Paper

Smart Altera firmware for DSP with FPGAs
Author(s): Uwe Meyer-Baese; A. Vera; A. Meyer-Baese; M. Pattichis; R. Perry
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Paper Abstract

Design of current DSP applications using state-of-the art multi-million gates devices requires a broad foundation of engineering skills ranging from knowledge of hardware-efficient DSP algorithms to CAD design tools. The requirement of short time-to-market, however, requires to replace the traditional HDL based designs by a MatLab/Simulink-based design flow. This not only allows the over 1 million MatLab users to design with FPGAs but also to by-pass the hardware design engineer and leads therefore to shorter development time. We have evaluated the Altera/Simulink tool flow used for a University design environment and present design experience of a semester course at FAMU-FSU College of Engineering. We discuss the required background knowledge, key target smart firmware for FPGAs and possible advanced designs, e.g. FFT and multirate filter banks and wavelets designed by students with only basic logic experience.

Paper Details

Date Published: 9 April 2007
PDF: 11 pages
Proc. SPIE 6576, Independent Component Analyses, Wavelets, Unsupervised Nano-Biomimetic Sensors, and Neural Networks V, 65760T (9 April 2007); doi: 10.1117/12.719017
Show Author Affiliations
Uwe Meyer-Baese, Florida State Univ. (United States)
A. Vera, Univ. of New Mexico (United States)
A. Meyer-Baese, Florida State Univ. (United States)
M. Pattichis, Univ. of New Mexico (United States)
R. Perry, Florida State Univ. (United States)


Published in SPIE Proceedings Vol. 6576:
Independent Component Analyses, Wavelets, Unsupervised Nano-Biomimetic Sensors, and Neural Networks V
Harold H. Szu; Jack Agee, Editor(s)

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