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Proceedings Paper

The calibration of process window model for 55-nm node
Author(s): Te Hung Wu; Sheng Yuan Huang; Chia Wei Huang; Pei Ru Tsai; Chuen Huei Yang; Irene Yi-Ju Su; Brad Falch
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Paper Abstract

In previous OPC model calibrations, most of the work was focused on how to calibrate a model for the best process conditions. With process tolerance decreasing in coming lithography generations, it is increasingly important to be able to predict pattern behavior through process window. Due to a low k1 factor that leads to a smaller process window, the use of process window models is required for both optical proximity correction (OPC) and Lithography Rule Check (LRC) applications to insure silicon success. In this paper, we would try to calibrate multiple process window models. The resulting models will be verified and judged using additional measurement data to demonstrate the quality.

Paper Details

Date Published: 26 March 2007
PDF: 10 pages
Proc. SPIE 6520, Optical Microlithography XX, 65203A (26 March 2007); doi: 10.1117/12.715496
Show Author Affiliations
Te Hung Wu, United Microelectronics Corp. (Taiwan)
Sheng Yuan Huang, United Microelectronics Corp. (Taiwan)
Chia Wei Huang, United Microelectronics Corp. (Taiwan)
Pei Ru Tsai, United Microelectronics Corp. (Taiwan)
Chuen Huei Yang, United Microelectronics Corp. (Taiwan)
Irene Yi-Ju Su, Synopsys, Inc. (Taiwan)
Brad Falch, Synopsys, Inc. (United States)


Published in SPIE Proceedings Vol. 6520:
Optical Microlithography XX
Donis G. Flagello, Editor(s)

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