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Proceedings Paper

Modelling and synthesis of automata in HDLs
Author(s): Sławomir Chmielewski; Marek Węgrzyn
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Paper Abstract

In the paper digital modelling and synthesis of automata in Hardware Description Languages is described. There is presented different kinds of automata and methods of realization using languages like VHDL and Verilog. Basic models for control units are: Finite State Machine (FSM), Algorithmic State Machine (ASM) and Linked State Machine (LSM). FSM, ASM and LSM can be represented graphically, which would help a designer to visualize and design in a more efficient way. On the other hand, a designer needs a fast and direct way to convert the considered designs into Hardware Description Language (HDL) codes for simulation and analysis it for synthesis and implementation.

Paper Details

Date Published: 12 October 2006
PDF: 14 pages
Proc. SPIE 6347, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2006, 63470J (12 October 2006); doi: 10.1117/12.714537
Show Author Affiliations
Sławomir Chmielewski, Univ. of Zielona Góra (Poland)
Marek Węgrzyn, Univ. of Zielona Góra (Poland)


Published in SPIE Proceedings Vol. 6347:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2006
Ryszard S. Romaniuk, Editor(s)

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