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Proceedings Paper

Clock-efficient and maintainable implementation of complex state machines in VHDL
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Paper Abstract

This paper presents a nonstandard approach to describe the complex state machines in VHDL to obtain both good readability of the code and efficient operation. This new approach, called "variable driven flow control in sequential process" allows to avoid loss of clock cycles when complex decisions are to be taken, and simultaneously allows to keep the structure of the code clear and easy to maintain. A simple example has been presented, showing the idea and practical implementation of the proposed method. The code produced by the presented method is synthesizable, and the obtained parameters of resulting FPGA implementation (both speed and occupancy) are good.

Paper Details

Date Published: 12 October 2006
PDF: 8 pages
Proc. SPIE 6347, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2006, 63470G (12 October 2006); doi: 10.1117/12.714532
Show Author Affiliations
Wojciech M. Zabolotny, Institute of Electronic Systems (Poland)


Published in SPIE Proceedings Vol. 6347:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2006
Ryszard S. Romaniuk, Editor(s)

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