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Proceedings Paper

EUVL mask substrate defect print study
Author(s): Jerry Cullins; Yoshihiro Tezuka; Iwao Nishiyama; Takeo Hashimoto; Tsutomu Shoki
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Paper Abstract

Mask substrate defects continue to be one of the critical issues for EUV technology development. Current specifications call for allowable defects in the 25nm height range for production masks blanks. Simulations seem to indicate that defects as small as 3nm high will cause printable defects on the wafer. To study the effects of small aspect defects on the printed image we undertook a study to look at 10nm height (mask substrate size) defects. A mask was fabricated with 12nm height defects in arrays based on area. Defects of 110nm, 190nm, 300nm, and 1000nm were fabricated. Multi-layers were then deposited and the mask was patterned with line/space patterns with pitches (mask size) of 600nm, 800nm, and 1000nm. Wafers were then exposed using a well characterized resist and the results were analyzed. All sizes of defects printed at least once. The largest defect size (1000nm mask) caused multiple bridges to form while even the smallest defect size (110nm mask) could cause a bridge on the 600nm (mask size) pitch.

Paper Details

Date Published: 15 March 2007
PDF: 9 pages
Proc. SPIE 6517, Emerging Lithographic Technologies XI, 65170E (15 March 2007); doi: 10.1117/12.714358
Show Author Affiliations
Jerry Cullins, Association of Super Advanced Electronics Technologies (Japan)
Yoshihiro Tezuka, Association of Super Advanced Electronics Technologies (Japan)
Iwao Nishiyama, Association of Super Advanced Electronics Technologies (Japan)
Takeo Hashimoto, Association of Super Advanced Electronics Technologies (Japan)
Tsutomu Shoki, HOYA Corp. (Japan)

Published in SPIE Proceedings Vol. 6517:
Emerging Lithographic Technologies XI
Michael J. Lercel, Editor(s)

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