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Proceedings Paper

Enabling immersion lithography and double patterning
Author(s): Kevin M. Monahan; Amir Widmann
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Paper Abstract

Most semiconductor manufacturers expect 193nm immersion lithography to remain the dominant patterning technology through the 32nm technology node. Conventional immersion lithography, however, is unlikely to take the industry to 32nm half-pitch. Various double patterning techniques have been proposed to address this limitation. These solutions will combine design for manufacturability (DFM) and advanced process control (APC) strategies to achieve desired yield. Each strategy requires feeding forward design and process context and feeding back process metrics. In this work, we discuss some interim solutions for control of double patterning lithography (DPL), as well as some spacer-etch alternatives. We conclude with focus-exposure data showing some potential challenges for pitch-splitting strategies implemented in the context of immersion lithography.

Paper Details

Date Published: 5 April 2007
PDF: 8 pages
Proc. SPIE 6518, Metrology, Inspection, and Process Control for Microlithography XXI, 65181M (5 April 2007); doi: 10.1117/12.714204
Show Author Affiliations
Kevin M. Monahan, Quantitative Yield Strategies (United States)
Amir Widmann, KLA-Tencor Corp. (United States)


Published in SPIE Proceedings Vol. 6518:
Metrology, Inspection, and Process Control for Microlithography XXI
Chas N. Archie, Editor(s)

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